A typical ferrite surface mount multilayer inductor includes a generally rectangular ferrite body with an electrically conductive path extending therethrough. The electrically conductive path, in turn, is connected to respective conductive coating layers on opposite ends of the ferrite body to facilitate connection to a printed circuit board, for example. Such a ferrite component may commonly be manufactured by printing a plurality of interconnected conductive traces on successive stacked ferrite layers.
U.S. Pat. No. 4,543,553 to Mandai et al. entitled "Chip-Type Inductor" discloses a chip inductor comprising a plurality of laminated magnetic layers. Linear conductive patterns extend between the respective magnetic layers, and these linear conductive patterns are connected successively to define a coil so as to produce an inductance component. The conductive patterns on opposite surfaces of the magnetic layers are connected to each other by through-holes or vias wherein the conductors are deformed to plunge through the holes to establish electrical contact.
Another device is disclosed in U.S. Pat. No. 4,689,594 to Kawabata et al. entitled "Multi-Layer Chip Coil." In this patent a multi-layer chip coil comprises a stack of intermediate layers of magnetizable material having a through-hole defined therein so as to extend completely through the thickness thereof. First and second patterned electrical conductors are formed on the opposite surfaces of each of the intermediate layers, and a hollow tubular conductive layer extends through the through-hole so as to connect adjacent conductors.
Still another device is disclosed in U.S. Pat. No. 5,302,932 to Person et al. entitled "Monolithic Multilayer Chip Inductor and Method For Making Same." This patent discloses a monolithic multilayer chip inductor which includes a plurality of subassemblies stacked one above another. Each of the intermediate subassemblies includes a ferrite layer having a coil conductor with a uniform width printed on its upper surface. The intermediate ferrite layers include via holes therein for permitting interconnection of the conductor coils from one layer to the other. In addition, one end of the top coil conductor is exposed adjacent the edge of the chip, and one end of the bottom coil conductor is exposed adjacent another end of the chip so that the conductors can be connected to end terminals. Unfortunately, great accuracy may be required in assembling the layers to provide sufficient electrical contact between each vertical conductor and the relatively narrow lateral conductors.
Pending U.S. patent application Ser. No. 08/445,475) entitled "High Current Ferrite Electromagnetic Interference Suppressor and Associated Method", and assigned to the assignee of the present invention, discloses a significant improvement in a ferrite inductor having high current handling capability. The laterally extending conductors may be made relatively thick and include enlarged width portions to connect to vertically extending electrical conductors. Unfortunately, the device may still become saturated at high currents, and, thus, be unable to provide a desired relatively high inductance at these higher operating currents as needed in certain applications.